Universal power gating kit to implement power domains in a single pass
Save energy partitioning your SoC into power islands whatever their content, and implement them in a single-pass using our CLICK fabric IP, with no risk of excessive in-rush current or wake-up time thanks to its patented Transition Ramp Cell.
Any Standard Cell Library
Its Power Management Cells
SESAME ICK (Islands Construction Kit) includes the cells required to support power gating, multi supply voltage and state retention techniques. Different ICK packages are available to match the cell height of the related SESAME standard cell library.
CLICK is library-independent (its cells do not need to be placed in a row) and can be applied to any domain whatever its nature (logic or hard macro) and origin (be it Dolphin Integration or an other IP provider). It is composed of specific Power Switches and a patented programmable Transition Ramp Controller (TRC) cell that controls automatically the in-rush current, enabling a fast and safe wake-up from sleep mode.
Our customers talk about the CLICK
Interview of Eric Flamand, CTO of Greenwaves Technologies, explaining how they adopted our CLICK in their first "IoT Processor".
Almost every device targeting the market today has low power requirements, be it a battery operated device or an fan-less device sensitive to heat dissipation.
Operating the whole design or some subsystems at a lower voltage enables to save dynamic power, while leakage power can be drastically reduced by shutting down unused parts of the design
Incremental solutions to save power consumption
…which can be used for any kind of power domain
Pure logic power domain
Apply to any logic library regardless of the cell height.
Apply to any hard macro: memory instance (ROM, SRAM or eFlash) and analog IP.
Composite power domain
Apply to any domain including a mix of logic block with some hard blocks.
Fitting power domain of any polygonal shape
CLICK key benefits
Flexible in-rush current management
Automated limitation of in-rush current, enabling a « correct-by-construction » implementation thanks to patented TRC cell
Short wake-up latency (hundreds of ns)
Easy tuning (hard and soft programmable) of “wake-up latency vs in-rush current” trade-off, even after tape-out
Single power gating solution at SoC level
- Applicable to any hard macro supplied at core voltage
- Applicable to any digital logic block whatever the library provider (e.g. 12T sponsored library)
Semi-automated and optimized power gating implementation thanks to dedicated scripts for sizing the switches, setting the maximum in-rush current allowed and creating the power switch ring around any polygonal voltage area.
Leakage power reduction
up to 99.9% leakage power saving in sleep modes
Multiple VT, channel length and switch height for reaching the best trade-off IR Drop vs. Leakage
Benefit from an optimum package when combined with SESAME & our ICK add-on
Power Performance Area (PPA)
A multi-VT solution
Allows low voltage operation and retention at very low voltage thanks to dedicated retention flops
Reduce dynamic power by lowering voltage / splitting into multiple voltage domains
Effective method for reducing leakage power in stand-by/sleep modes (by switching-off unused blocks)
Area optimization thanks to the compatibility with our ultra High Density libraries (Sesame uHD) through dedicated retention spinner cells.
To shut down a block without losing register contents
Fast method to get the block fully functional after wake up (resume operation in hundreds of ns)
Capability to control always-on signals in power-gated blocks
Even better with our unique Fabric IPs...
Transition Ramp Controller for a safe power-up sequence
TRC (Transition Ramp Controller) is a unique patented cell providing a self-regulated and reliable way to control the power-on sequence. During wake-up, the TRC controls the voltage level applied at the transistor gate to open progressively the power switches.
With TRC, in-rush current is automatically clamped to the maximum allowed (up to 8 power-on scenarios are dynamically programmable), providing the twofold advantage of avoiding IR drop issue and optimizing wake-up latency.
Our TRC enables:
- Automated limitation of in-rush current
- Max in-rush current value is dynamically controllable enabling a management of power-on sequence by software, after tape-out.
- Iterative and complex in-rush current analysis is replaced by a single verification
Thanks to the TRC, the in-rush current is kept below a safe limit ensuring a limited voltage drop
- Smart "control” of the trade-off between wake-up time and in-rush current
- Semi-automated power-on sequence including isolation and retention signal management
CLICK deliverables include scripts for an automatic power switch ring insertion and default TRC configuration.
The TRC of each power domain must be explicitly declared in Verilog. When used with Maestro, our unique solution to build the embedded power control network, TRC instantiation is automatically managed (transparent for the SoC designer).
SRAM with ERS option (Embedded Retention and Shutdown switches) embed a TRC to safely handle the wake up from retention and shut-down modes. Learn more...