Why is a control network needed?
Ultra low-power optimization is required to meet the growing requirements for long battery life of ever more feature-rich and power consuming mobile applications. The functions of the SoC need to be available whenever they are needed while not causing battery drain when not used.
- The question is how to design a SoC meeting such low-power constraints?
- Partitioning the SoC into voltage and power domains enables turning on and off different functions of a SoC for extreme power optimizations leveraging clock distribution and power domain construction techniques.
An embedded control network is needed to manage wisely the distribution of clocks and regulated voltages, to handle start and wake-up sequences, as well as to operate safe transitions between power modes as functions are switched on or off.
- Partitioning the SoC into voltage and power domains enables turning on and off different functions of a SoC for extreme power optimizations leveraging clock distribution and power domain construction techniques.
The conventional approach consists in developing a monolithic and full custom Activity Control Unit (ACU) or Power Management Unit (PMU / PMU logic). Such an ACU/PMU is complex to develop with its connections to all power islands and associated resources, tedious to validate and little amenable to architectural updates.
Here comes Maestro™!
Our customers talk about MAESTRO
Interview of Eric Flamand, CTO of Greenwaves Technologies, explaining how they adopted MAESTRO in their first "IoT Processor".
What is Maestro?
Maestro™ is an embedded SoC control fabric providing the means to the RTL designer to safely design the control of power island domains along with their voltage regulators and clocks.
Maestro™ is a set of generic Verilog RTL modules, with adaptable interfaces to resources, to implement the Activity Control Unit (ACU) or Power Management Unit (PMU / PMU logic) of any SoC, whatever its complexity, and to replace “hand-made” solutions.
Maestro™ is the easiest solution to manage power domains and power state transitions!
"Compared to the design of a monolithic SoC activity controller,
the modular approach provided by Maestro enables easy architectural changes for low-power optimization,
such as grouping or splitting of power islands or updating the power management network for improving the Figure-of-Merit of the SoC, without jeopardizing the design of the SoC activity controller."
Lead Architect
Key Benefits of Maestro™, the bandmaster of your SoC
Safe design implementation
Application of the subsidiarity principle which eliminates the risk of “conflict of modes” between shared voltage regulators and clock generators
Module hierarchy matching the power-management network hierarchy
Flexible and modular design
Synthesizable Verilog RTL modules, with adaptable interfaces to voltage regulators and clock generators
Scalable with the increase of SoC complexity (number of power islands and modes)
Time saving
Reusable Verilog RTL modules with guidelines for network assembly
Quick adaptation/upgrade of the embedded control network to SoC architectural updates
Easy reprogramming of mode switching thanks to a software C/C++ state machine
Power consumption optimization
Easy implementation of power island control thanks to generic Verilog RTL modules
Minimum logic required to be supplied in the Always-On Domain
High reliability
Already implemented in complex SoC
Test compliant and testable with controlled power island state for scan
TSMC Soft IP9000 qualification
More flexible and reusable than a "hand-made" ACU/PMU-Logic solution while enabling faster development of the mode switching program than a full C/C++ solution
Maestro™ principles
Modular approach
Reduce ACU/PMU-logic development complexity thanks to:
- Mode switching Program (C/C++) for software implementation of state machine to manage mode changes
- Hardware (RTL) central activity controller which manages boot, start-up and extinction sequences
- Hardware (RTL) local activity controller which changes the power-island mode and transmits request to the shared resource manager
- Hardware (RTL) resource manager which manages the resource state and request conflicts
Dedicated control bus
- With a simple communication protocol for mode change requests
- To enable the construction of the power island architecture over the functional block architecture
- To avoid congestion on the data/system bus
- To save power by switching off the data/system bus in deep-sleep modes
Benefits compared to a NoC solution
NoC solutions are designed for complex data flow management in SoCs with multiple processors and on-chip network communication.
Maestro™ is geared towards power and clock control in ultra low-power SoCs
Streamline the low-power SoC design flow
Simplification of critical steps of the low-power SoC design flow:
- SoC specification
- Power island architecture
- SoC activity control unit design
- Hardware and software partition and development
- Etc.
Discover our voltage regulator offering, per the DELTA standard, to assemble any SoC power management network, best when managed by Maestro™
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