A comprehensive offering of Standard Cell libraries
Dolphin Integration standard cell libraries have been designed to provide an area effective solution for the ever growing stringent low-power requirements of embedded systems.
The SESAME offering is thus organized around a variety of libraries optimized for providing the best area and the minimum power for either main digital logic blocks or always-on logic. The libraries are complemented with power management cells whenever required.
Relying on a unique and stringent qualification process, SESAME libraries are available from 180 nm down to 22 nm in several foundries and process variants.
Quality and performances of SESAME libraries have been acknowledged by several foundries who selected our libraries to be part of their foundry sponsored program / ecosystem.
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Libraries for Always-on domains
The Always-On Domain is the subset of the design that is supplied first and remains powered, whatever the mode, until the whole circuit is completely shut-down.
The Always-On Domain aims at providing the means to wake-up from "sleep" modes and resume normal operation. It includes an always-active logic block ("always-on logic") that needs to be kept active to process the events used to trigger the wake-up of the whole device, along with the related infrastructure (power supply, clock, I/O...). The Always-on logic typically includes an internal trigger, such as a Real-Time-Clock (RTC), a system to process external events (e.g. wake-up interrupt controller) and some logic (usually called ePMU - embedded Power Management Unit) to turn on the functional blocks that have been powered-down during sleep mode.
In applications with a low duty cycle (such as Wearables) where the circuit is in sleep mode most of the time, it is pivotal to minimize the power consumption of the always active logic. Hence, Dolphin Integration offers two standard-cell libraries specifically designed to meet the low-power needs of the always-on block in different application contexts.
SESAME BIV
Standard cell library based on thick-gate oxide devices providing significant leakage savings compared to standard devices.
- Enabling removal of a voltage regulator due to wide operation range (up to 3.3 V +/-10% and down to 1.2 V +/-10%) support, which allows a direct connection to batteries.
- It can also be used to implement a small logic block in an analog voltage domain.
SESAME NTV
Near Threshold Voltage library with low-voltage capability enabling near-Vt operation for drastic power consumption reduction.
- Optimized at schematic level with a patented flip-flop for safe low-voltage operation.
- Thanks to its near threshold characterization (down to 0.75 V at 55 nm) this library allows to share a regulator between the Always-on logic and memories in retention mode.
Main logic libraries: 4 complementary libraries
SESAME 9T
Balanced P.P.A library for best trade-off between density and speed.
SESAME HD
High density library for optimal area reduction on medium/low speed design.
SESAME uHD
Ultra high density relying on ultra dense flip-flop for achieving the world’s best density with minimum power consumption.
SESAME eLC
Extremely low power consumption for achieving the minimum power consumption.
ZOOM on SESAME uHD and its Spinner System
SESAME uHD library relies on the "spinner cell" as a denser substitute to the standard Flip-Flop in order to achieve up to 15% overall area saving. The spinner cell is an optimized latch. When combined with a pulse generator to create a short pulse on its clock input, it becomes a "pulsed latch", functionally equivalent to a Flip-Flop.
The added value of SESAME uHD library is thus to provide the benefit of both area and power consumption savings, based on our silicon proven pulsed latch technique, while being fully compliant with standard design flows (full support of Cadence and Synopsys EDA solutions).
This library, available from 180 nm down to 28 nm, has been already adopted by many customers thanks to its proven cost-effective approach.
Technical papers about the spinner system
How to reduce up to 99.9% the leakage of your SoC?
At SoC architecture level, "multi-VDD" and "power-gating" are the most efficient techniques to save power.
A multi-voltage design is based on splitting a design into multiple-voltage-islands supplied at different voltage levels to save dynamic power.
Power-gating techniques enable to switch-off (independently) the power-supply of parts of the circuit that are not in use to reduce leakage power.
The support for these design techniques requires the usage of specific cells not included in regular standard cell libraries.
These power management cells are packaged in an add-on module called SESAME ICK (Island Construction Kit).
It is then enhanced by the CLICK that features the patented programmable Transition Ramp Controller (TRC) cell to provide a fast and safe wake-up from sleep mode with an automatic limitation of in-rush current.
Key Benefits of all our standard cell libraries
Maximum density
- Handcrafted cell layout for highest density and best routability
- Tap-less cell using M1 power rail (Metal 2 is fully available for routing)
Minimum Power
- Multi-Vt library for combining performance with low power
- Multi-channel cells for significant leakage reduction with same footprint
- Support of low power (UPF and CPF) EDA design flows.
- Multi-VDD characterization (overdrive/low voltage support)
Comprehensive solution
- Electrically, physically and EDA-view aligned with memory products and voltage regulators
- Support for major EDA flows (Cadence, Synopsys...)
- Custom PVT support
Standard Cell Evaluation
Performance overview
Get a quick comparison thanks to our six cell based benchmark called "SOFIA" benchmark.
Assessment
Assess the performances thanks to our evaluation kits
- To get quick access to the results of our libraries with our public RTL benchmark: Motu-Uta
Support
Benefit from our technical support all along your evaluation process
Zoom on Motu-Uta Benchmark
For a complete comparative evaluation of libraries from topological synthesis to Placement and Routing, the Motu-Uta logic standard (logic block in RTL) is proposed. Available publicly as freeware, Motu-Uta embeds a pseudo co-processor, different critical paths and combinatorial logic, representation of a typical logic block in all dimensions: area, power consumption and speed, while avoiding mistakes due to the misreading of a proprietary standard.
In order to provide a fair comparison in terms of power consumption, a test bench called TSUNAMI is provided to generate the activity file for the power estimation.
Click here to request Motu-Uta results for SESAME libraries in your targeted process
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Latest news
2017/02 - Technical publication: Standard cell libraries for Always-On Domain
2016/09 - Amazing improvement of power and density for RFID chips with standard cell libraries at 180 nm
2016/07 - Save up to 20 % of silicon area with our standard cell library SESAME uHD
2016/05 - Technical publication: Methodology to lower supply voltage of standard cell libraries
2016/05 - Try and adopt Motu-Uta, the benchmark for a fair evaluation of Standard Cell libraries
2016/01 - Optimize the power of always-on logic with SESAME NTV library in TSMC 55 uLP / uLP-eF process
