Catalog of Cache Controller
Product:R-Stratus-LPRR
Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
R-Stratus-LPRR is THE new generation of cache controller for MCU applications whenever the application program is stored in a Non Volatile Memories (NVM) like eFlash or EEPROM.
R-Stratus LPRR provides the twofold advantage of speed improvement and of power consumption minimization.
AMBA 3 AHB-lite compliant.
R-Stratus LPRR includes a Retention Ready feature to allow fast CPU wake-up from deep sleep mode.
Key Benefits of R-Stratus-LPRR
- TSMC Soft IP qualification (IP9000)
- Straightforward connection
- Support of AHB-Lite interfaces to ensure fast and smooth integration in any MCU subsystem without need for any bridge
- External TAG and Cache memories to improve portability across a wide range of process technologies
- Standard interface for TAG and Cache memories
- Performance optimization (optional)
- Highly user configurable cache controller (associativity, cache line size, critical word first...) simplified with Smartvision for checking in simulation that the configuration is optimal for achieving the best speed and power consumption
- Improvement of processing power
- Apparent frequency is accelerated up to 11 times
- Zero wait state for cache hit
- Critical word first to reduce the number of cycles in case of miss
- First cache controller optimized for low power
- Architecture designed to minimize the number of accesses to TAG and cache RAM and NVM
- Runtime programmable cache line size and associativity
- Up to 14 times less power consuming!
Get access to the complete product primer of R-Stratus-LPRR
Key Features and Performances
*Evaluation conditions
Use of the high density and power optimized Sesame libraries from Dolphin Integration
Configuration: CPU + 1 timer + I/O ports
SS, Vdd-10%, 125°C, 50 MHz
post-synthesis (no P&R) with clock gating, no scan insertion
Peripherals
To suit all user requirements, the set of peripherals delivered with R-Stratus-LPRR is entirely configurable.
Among its peripheral offering, Dolphin Integration can provide R-Stratus, a cache controller enabling speed improvement and power consumption minimization when using Non Volatile Memories (eFlash, EEPROM...)
Applications
AR - VR;Automotive;Bluetooth;Cellular IoT;GNSS;Hearing aids;Home Appliance;Infotainment;NB-IoT;Smart Headset;Smart Speaker;TWS Earpods;ULP MCU;Voice-controlled devices;Voice Assistant;WiFi
Development tools
BIRD Falcon on-chip debugger for hardware debug
- Scalable embedded debug solution enabling to achieve the optimal trade-off between debugging features and silicon cost
Related products
Libraries of Standard cells and memories
- optimized for high density and low power consumption
- enabling island partitioning
Power regulators to build an optimized SoC architecture for the lowest power consumption
High resolution analog converters for audio or measurement applications
Deliverables
- Verilog or VHDL netlist
- Source code (optional)
- Testbench with documentation for checking the functionality of any configuration of the Flip80251 Hurricane at any representation level (RTL down to silicon).
Robustness is ensured
For more than 15 years, Dolphin Integration has built a testsuite for checking the functionality of any configuration of the R-Stratus-LPRR at any representation level (RTL down to silicon).The testbenches have evolved a lot thanks to users feedback.
The testbench is delivered with its documentation to our microcontroller core users so that they can apply it on their own project and ensure functionality.