Embedded memory IP: Single-Port SRAMs

SpRAM RHEA DV

REACH THE HIGHEST DENSITY
Thanks to smart periphery design
Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
Using Pushed Rules Foundry bitcell
EXTEND BATTERY LIFE
Designed with partitioned array to reach ultra low power consumption at 1.2 V +/-10% and 0.9 V +/-10%
Support a couple of power saving modes: stand by and data retention mode
Minimum data retention mode for ultra low leakage saving: 0.55 V +/-10% (optional)
MAKE INTEGRATION EASIER
MUX option enabling several performance tradeoffs and form factor
Data range flexibility allows easy addition of bits for ECC purposes
Address range flexibility allows easy addition of single rows for redundancy purposes
Embedded extinction&retention switchs (ERS optional)
ENABLE RIGHT ON FIRST PASS DESIGN
Complete mismatch validation of the memory architecture taking in account local and global dispersion
Extended validation for high coverage rate of the compiler
DECREASE TIME TO MARKET
Multi foundries support using the same architecture

Variants

VT Bit cell

VT Periphery

Operating Voltage

Capacity

Option mode

55 uLP eFlash

eHVT

HVT
SVT

Nominal voltage:
1.2 V +/-10% and 1.3V +/-10%

Low voltage:
0.9 V +/-10% and 1.0 V +/-10% and 1.1 V +/-10%

256 bits - 320 Kbits